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74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 03 -- 14 September 2005 Product data sheet
1. General description
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop.
2. Features
s Multiple package options s Complies with JEDEC standard no. 7A s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specified from -40 C to +85 C and from -40 C to +125 C
3. Applications
s Frequency dividing circuits s Time delay circuits s Control counters
4. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Qn to Qn+1 CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V 14 8 ns ns Conditions Min Typ Max Unit Type 74HC4040
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 1: Quick reference data ...continued GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol fmax Ci CPD Parameter maximum operating frequency input capacitance power dissipation capacitance propagation delay CP to Q0 Qn to Qn+1 fmax Ci CPD maximum operating frequency input capacitance power dissipation capacitance VI = GND to VCC - 1.5 V CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V 16 8 79 3.5 20 ns ns MHz pF pF VI = GND to VCC Conditions CL = 15 pF; VCC = 5 V Min Typ 90 3.5 20 Max Unit MHz pF pF
Type 74HCT4040 tPHL, tPLH
[1]
CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V.
5. Ordering information
Table 2: Ordering information Package Temperature range 74HC4040N 74HC4040D 74HC4040DB 74HC4040PW 74HC4040BQ -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C Name DIP16 SO16 SSOP16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-1 SOT109-1 Type number
plastic shrink small outline package; 16 leads; body SOT338-1 width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm DIP16 SO16 plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm SOT38-1 SOT109-1
74HCT4040N 74HCT4040D
-40 C to +125 C -40 C to +125 C
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
2 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 2:
Ordering information ...continued Package Temperature range Name SSOP16 TSSOP16 Description Version plastic shrink small outline package; 16 leads; body SOT338-1 width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Type number
74HCT4040DB -40 C to +125 C 74HCT4040PW -40 C to +125 C 74HCT4040BQ -40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm
6. Functional diagram
CP MR
10 11
T 12-STAGE COUNTER CD 9 7 6 5 3 2 4 13 12 14 15 1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig 1. Functional diagram
CTR12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 9 7 6 5 3 2 4 13 12 14 15 1 10 11 + CT = 0 0 9 7 6 5 3 2 4 13 12 14 15 1
10
CP
CT
11
MR
11
001aad585
001aad586
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
3 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
CP
FF T1
Q
FF T2
Q
FF T3
Q
FF T4
Q
FF T5
Q
FF T6
Q
Q RD MR RD
Q RD
Q RD
Q RD
Q RD
Q
Q0
Q1
Q2
Q3
Q4
Q5
FF T7
Q
FF T8
Q
FF T9
Q
FF T 10
Q
FF T 11
Q
FF T 12
Q
Q RD RD
Q RD
Q RD
Q RD
Q RD
Q
Q6
Q7
Q8
Q9
Q10
Q11
001aad588
Fig 4. Logic diagram
7. Pinning information
7.1 Pinning
terminal 1 index area Q11 Q5 Q4 Q6 Q3 Q2 Q1 GND 1 2 3 4 5 6 7 8
001aad583
16 VCC 15 Q10 14 Q9 13 Q7 12 Q8 11 MR 10 CP 9 Q0
Q5 Q4 Q6 Q3 Q2 Q1
2 3 4 5 6 7 8 GND Q0 9
16 VCC 15 Q10 14 Q9 13 Q7 12 Q8 11 MR 10 CP
4040
GND(1)
1
Q11
4040
001aad584
Transparent top view
(1) The substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input
Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16
Fig 6. Pin configuration DHVQFN16
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
4 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
7.2 Pin description
Table 3: Symbol Q11 Q5 Q4 Q6 Q3 Q2 Q1 GND Q0 CP MR Q8 Q7 Q9 Q10 VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description output 11 output 5 output 4 output 6 output 3 output 2 output 1 ground (0 V) output 0 clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) output 8 output 7 output 9 output 10 positive supply voltage
8. Functional description
8.1 Function table
Table 4: Input CP X
[1]
Function table Output MR L L H Q0 to Q11 no change count L
H = HIGH voltage level; L = LOW voltage level; X = don't care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
5 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
8.2 Timing diagram
1 CP input MR input Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad587
2
4
8
16
32
64
128
256
512 1024 2048 4096
Fig 7. Timing diagram
9. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input diode current output diode current output source or sink current quiescent supply current ground current storage temperature power dissipation DIP16 package SO16, SSOP16, TSSOP16 and DHVQFN16 packages
[1]
Conditions VI < -0.5 V or VI > VCC + 0.5 V VI < -0.5 V or VI > VCC + 0.5 V -0.5 V < VO < VCC + 0.5 V
Min -0.5 -65
Max +7 20 20 25 50 50 +150 750 500
Unit V mA mA mA mA mA C mW mW
Tamb = -40 C to +125 C
[1]
-
For DIP16 packages: above 70 C, Ptot derates linearly with 12 mW/K. For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 C, Ptot derates linearly with 8 mW/K.
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
6 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
10. Recommended operating conditions
Table 6: Symbol VCC VI VO Tamb tr, tf Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input rise and fall times see Section 11 and 12 per device except for Schmitt-trigger inputs VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V type 74HCT4040 VCC VI VO Tamb tr, tf supply voltage input voltage output voltage ambient temperature input rise and fall times see Section 11 and 12 per device except for Schmitt-trigger inputs VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 6.0 500 ns ns ns 4.5 0 0 -40 5.0 5.5 VCC VCC +125 V V V C 6.0 1000 500 400 ns ns ns Conditions Min 2.0 0 0 -40 Typ 5.0 Max 6.0 VCC VCC +125 Unit V V V C
type 74HC4040
11. Static characteristics
Table 7: Static characteristics for 74HC4040 Voltages are referenced to GND (ground = 0 V). Symbol Tamb = 25 C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4.0 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 V V V V V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 V V V V V V Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
7 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 7: Static characteristics for 74HC4040 ...continued Voltages are referenced to GND (ground = 0 V). Symbol VOL Parameter LOW-level output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILl ICC CI VIH input leakage current quiescent supply current input capacitance HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4.0 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V; VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILl ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V 0.1 0.1 0.1 0.33 0.33 1.0 80.0 V V V V V A A 1.9 4.4 5.9 3.84 5.34 V V V V V VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 1.5 3.15 4.2 3.5 0.5 1.35 1.8 pF V V V V V V Tamb = -40 C to +85 C 0 0 0 0.15 0.16 0.1 0.1 0.1 0.26 0.26 0.1 8.0 V V V V V A A Min Typ Max Unit
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
8 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 7: Static characteristics for 74HC4040 ...continued Voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4.0 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V; VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILl ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0.1 0.1 0.1 0.4 0.4 1.0 160.0 V V V V V A A 1.9 4.4 5.9 3.7 5.2 V V V V V Min Typ Max Unit
Table 8: Static characteristics for 74HCT4040 Voltages are referenced to GND (ground = 0 V). Symbol Tamb = 25 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL IO = -20 A; VCC = 4.5 V IO = -4.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 4.0 mA; VCC = 4.5 V ILl ICC ICC input leakage current quiescent supply current additional quiescent supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A CP MR CI VIH VIL input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Tamb = -40 C to +85 C 2.0 0.8 V V 85 110 3.5 306 396 A A pF 0 0.15 0.1 0.26 0.1 8.0 V V A A 4.4 3.98 4.5 4.32 V V 2.0 1.6 1.2 0.8 V V Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
9 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 8: Static characteristics for 74HCT4040 ...continued Voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions VI = VIH or VIL IO = -20 A; VCC = 4.5 V IO = -4.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 4.0 mA; VCC = 4.5 V ILl ICC ICC input leakage current quiescent supply current additional quiescent supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A CP MR Tamb = -40 C to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL IO = -20 A; VCC = 4.5 V IO = -4.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 4.0 mA; VCC = 4.5 V ILl ICC ICC input leakage current quiescent supply current additional quiescent supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A CP MR 417 539 A A 0.1 0.4 1.0 160.0 V V A A 4.4 3.7 V V 2.0 0.8 V V 383 495 A A 0.1 0.33 1.0 80.0 V V A A 4.4 3.84 V V Min Typ Max Unit
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
10 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
12. Dynamic characteristics
Table 9: Dynamic characteristics for type 74HC4040 GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Tamb = 25 C tPHL, tPLH propagation delay CP to Q0 see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF VCC = 6.0 V; CL = 50 pF propagation delay Qn to Qn+1 see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF VCC = 6.0 V; CL = 50 pF tPHL propagation delay MR to Qn see Figure 8 VCC =2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tTHL, tTLH output transition time see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tW clock pulse width HIGH or LOW see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF master reset pulse width; HIGH see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF trec recovery time MR to CP see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF fmax maximum operating frequency see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF VCC = 6.0 V; CL = 50 pF CPD power dissipation capacitance 6.0 30 35 27 82 90 98 20 MHz MHz MHz MHz pF 50 10 9 8 3 2 ns ns ns 80 16 14 22 8 6 ns ns ns 80 16 14 14 5 4 ns ns ns 19 7 6 75 15 13 ns ns ns 61 22 18 185 37 31 ns ns ns 28 10 8 8 100 20 17 ns ns ns ns 47 17 14 14 150 30 26 ns ns ns ns Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
11 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 9: Dynamic characteristics for type 74HC4040 ...continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Conditions see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF propagation delay Qn to Qn+1 see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tPHL propagation delay MR to Qn see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tTHL, tTLH output transition time see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tW clock pulse width HIGH or LOW see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF master reset pulse width; HIGH see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF trec recovery time MR to CP see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF fmax maximum operating frequency see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF 4.8 24 28 MHz MHz MHz 65 13 11 ns ns ns 100 20 17 ns ns ns 100 20 17 ns ns ns 95 19 16 ns ns ns 230 46 39 ns ns ns 125 25 21 ns ns ns 190 38 33 ns ns ns Min Typ Max Unit Tamb = -40 C to +85 C
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
12 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 9: Dynamic characteristics for type 74HC4040 ...continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Conditions see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF propagation delay Qn to Qn+1 see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tPHL propagation delay MR to Qn see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tTHL, tTLH output transition time see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF tW clock pulse width HIGH or LOW see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF master reset pulse width; HIGH see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF trec recovery time MR to CP see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF fmax maximum operating frequency see Figure 8 VCC = 2.0 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF VCC = 6.0 V; CL = 50 pF
[1] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V.
Min
Typ
Max
Unit
Tamb = -40 C to +125 C 120 24 20 120 24 20 75 15 13 4.0 20 24 225 45 38 150 30 26 280 56 48 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
13 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 10: Dynamic characteristics for type 74HCT4040 GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Tamb = 25 C tPHL, tPLH propagation delay CP to Q0 see Figure 8 VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF propagation delay Qn to Qn+1 see Figure 8 VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF tPHL tTHL, tTLH tW propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH trec fmax recovery time MR to CP maximum operating frequency VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; see Figure 8 VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance per package propagation delay CP to Q0 propagation delay Qn to Qn+1 tPHL tTHL, tTLH tW propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH trec fmax recovery time MR to CP maximum operating frequency VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8; VCC = 4.5 V; CL = 50 pF; see Figure 8
[1]
Parameter
Conditions
Min
Typ
Max
Unit
16 16 10
19 16 10 8 23 7 7 6 2
40 20 45 15 -
ns ns ns ns ns ns ns ns ns
30 -
72 79 20
-
MHz MHz pF
Tamb = -40 C to +85 C tPHL, tPLH 20 20 13 24 50 25 56 19 ns ns ns ns ns ns ns MHz
Tamb = -40 C to +125 C tPHL, tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 60 30 ns ns
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
14 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 10: Dynamic characteristics for type 74HCT4040 ...continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol tPHL tTHL, tTLH tW Parameter propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH trec fmax recovery time MR to CP maximum operating frequency Conditions VCC = 4.5 V; CL = 50 pF; see Figure 8 VCC = 4.5 V; CL = 50 pF; see Figure 8 VCC = 4.5 V; CL = 50 pF; see Figure 8 VCC = 4.5 V; CL = 50 pF; see Figure 8 VCC = 4.5 V; CL = 50 pF; see Figure 8 VCC = 4.5 V; CL = 50 pF; see Figure 8 Min 24 24 15 20 Typ Max 68 22 Unit ns ns ns ns ns MHz
[1]
CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V.
13. Waveforms
VI MR input VM tW trem VI CP input tW VM 1/fmax
tPHL Q0 or Qn output
tPLH
tPHL VM
tTLH
tTHL
001aad590
74HC4040: VM = 50 %; VI = GND to VCC. 74HCT4040: VM = 1.3 V; VI = GND to 3 V.
Fig 8. Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition times, maximum clock pulse frequency, master reset (MR) pulse width, master reset to output (Qn) propagation delays and master reset to clock (CP) removal time.
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
15 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
VCC PULSE GENERATOR VI DUT RT CL
mna101
VO
Definitions for test circuit: CL = load capacitance including jig and probe capacitance (See Section 12 for the value). RT = termination resistance should be equal to output impedance ZO of the pulse generator.
Fig 9. Test circuit
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
16 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
14. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.02 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001 JEITA SC-503-16 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 10. Package outline SOT38-1 (DIP16)
74HC_HCT4040_3 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
17 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT109-1 (SO16)
74HC_HCT4040_3 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
18 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT338-1 (SSOP16)
74HC_HCT4040_3 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
19 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 13. Package outline SOT403-1 (TSSOP16)
74HC_HCT4040_3 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
20 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 7 vMCAB wM C y1 C
C y
1 Eh 16
8 e 9
15 Dh
10 X 2.5 scale 5 mm
0
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 14. Package outline SOT763-1 (DHVQFN16)
74HC_HCT4040_3 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
21 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
15. Revision history
Table 11: Revision history Release date 20050914 Data sheet status Product data sheet Change notice Doc. number Supersedes 74HC_HCT4040_CNV_2 Document ID 74HC_HCT4040_3 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors Reference to family specifications is replaced by the actual information: Section 5 "Ordering information", Section 7 "Pinning information", Section 9 "Limiting values", Section 10 "Recommended operating conditions", Section 11 "Static characteristics", Figure 9 "Test circuit" Section 14 "Package outline" (DHVQFN16) added Product specification -
*
74HC_HCT4040_CNV_2 19901231
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
22 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
16. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
19. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74HC_HCT4040_3
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 14 September 2005
23 of 24
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
21. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 10 11 12 13 14 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information . . . . . . . . . . . . . . . . . . . . 23
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 September 2005 Document number: 74HC_HCT4040_3
Published in The Netherlands
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